IBM's nanostack demo puts nearly 100 billion transistors on a fingernail of silicon

Sub-1nm chip technology has a working demo. IBM unveiled its nanostack architecture on June 25, 2026, and the images went viral this week.

What a nanostack is

A transistor is a microscopic switch controlling electricity inside a chip, and billions of them run your phone. In IBM’s nanostack design, each transistor channel is built from three nanosheets, each roughly 15 atoms thick and spaced 9 nanometers apart. The transistors themselves are then bonded in vertical layers, instead of only being shrunk sideways as chipmaking has done for decades.

The result: nearly 100 billion transistors fit onto silicon about the size of a fingernail, with up to 50% more performance or 70% better energy efficiency compared with IBM’s 2nm node.

The caveats that matter

Two things keep this honest. First, IBM calls it the world’s first sub-1nm chip technology, but the 0.7nm label is a node name, not a physical measurement, and researchers have publicly pushed back on the framing. Node names stopped describing actual feature sizes years ago.

Second, this is a lab result, not a product. IBM targets commercial use within five years, and the company no longer manufactures chips itself, so someone else would have to build it at scale. Experts quoted by MIT Technology Review expect wide deployment closer to a decade out.

Why it still matters

Even with those asterisks, the demo lands in the middle of the biggest question in hardware: whether transistor density can keep improving as sideways shrinking runs out of room. Going vertical is the industry’s favored answer, and IBM has now shown a working version of what that looks like at the extreme end.

Whether this buys Moore’s Law another decade is exactly the argument the viral images have reignited. The physics says maybe. The manufacturing timeline says be patient.